Double precision floating-point arithmetic on FPGAs
نویسندگان
چکیده
We present low cost FPGA floating-point arithmetic circuits for all the common operations, i.e. addition/subtraction, multiplication, division and square root. Such circuits can be extremely useful in the FPGA implementation of complex systems that benefit from the reprogrammability and parallelism of the FPGA device but also require a general purpose arithmetic unit. While previous work has considered circuits for low precision floating-point formats, we consider the implementation of 64-bit double precision circuits that also provide rounding and exception handling. Double Precision Floating-Point Arithmetic on FPGAs Stavros Paschalakis Peter Lee Mitsubishi Electric ITE BV VI-Lab University of Kent at Canterbury E-mail: [email protected] E-mail: [email protected]
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